(1) Field of the Invention
The present invention relates in general to semiconductor manufacturing, and in particular, to the design of a seal-ring like structure at wafer edge to eliminate problems caused by the formation of complex layers at the edge.
(2) Description of the Related Art
Manufacturing of semiconductor substrates encompasses hundreds of different process steps. The steps involve creating patterns, introducing dopants, and depositing films on a silicon substrate repetitively throughout the manufacturing process to form integrated structures. Because the various structures that are built on a substrate or a wafer are serial in natures that is, that they are built one on top of another in a sequential manner, it becomes very important that each layer of structure is substantially defect free before the next one is placed thereon.
Defects are generally caused when an unwanted particulate matter unintentionally lands between features on a layer and "bridges" or connects them, and therefore, disables them by "shorting" under certain conditions; or when an unwanted particulate matter lands on a feature, and disables it by creating an unwanted "open" in the circuitry. The size of the particulates in relation to the size o the features play an important role in creating the defects. As the size of features in today's high density integrated circuit chips (IC) are getting miniaturized ever so incessantly, control over the size of contaminants introduced into the manufacturing line need also be scrutinized diligently if acceptable levels of yield are to be maintained. Thus, for submicron lithographic technologies where the wiring features or patterns are less than one micrometer, .mu.m, in width, the size of the invading particulate matter need be controlled to between about one fifth to one tenth of the width, or between about 0.1-0.25 .mu.m. With chip sites of about 5 mm.times.5 mm on a wafer, or of an area of 25 mm.sup.2, the allowable defect density is about 0.02 pieces/mm.sup.2 in order to achieve satisfactory levels of yield. For larger chip areas on the order of 100 mm.sup.2, the defect density must be below 0.003 pieces/mm.sup.2 in order to achieve the same yield.
Defects can best be avoided if the sources of the contaminants or dust particles are eliminated. There are mainly two major sources for contaminants that are introduced into a manufacturing line: the first one is that which resides outside the work piece, namely the wafer, such as the ambient air surrounding the wafer, or fluids, such as chemicals, that are brought to the work piece for various processes that take place at the work-station. These contaminants that are external to the work piece and sometimes are known as "drop-ons", can generally be kept away from the work-piece by proper use of filters, and other implements that are commonly available. The other source for particle contaminants is the work piece itself, and the contaminants generated from the work-piece is sometimes referred to as being "process-induced." As work is being performed on the work-piece, the work-piece releases particulate matter, or dust, due to abrasion or breakage caused by excessive stresses imposed on certain parts of the work-piece. A case in point is when a wafer, for example, is clamped down or held on the edges by wafer holders, tweezers and the like. As expected, they are usually the corners, edges, and other such places on the work-piece that are subjected to large stresses resulting from their small areas.
Due to the complexity of piling structure at wafer edge, the breakage at the edge becomes more pronounced because of the various different layers of materials that are deposited in building the structure on silicon or other semiconductor substrates. Furthermore, since the properties of the materials vary considerably from layer to layer, such as for example, from metals for interconnection layers, to different types of dielectrics for interlevel layers, the nature of breakage of each one of the materials vary from each other, and consequently, the size of the particulate matter that are released as a result of such breakages also varies. In prior art, several attempts have been made to control the amount of such breakage as explained below.
A common approach for controlling the amount of breakage or peeling from the edge of a wafer has been to chamfer the edge. This chamfering or rounding off the edge of the substrate in advance, prior to performing the subsequent process steps has been successful in reducing particles that would be generated from the substrate edge itself. Special techniques such as disclosed in U.S. Pat. No. 5,425,846 have been developed to remove material from the periphery of wafers for this purpose. Usually, the substrate at this stage has already, built in it the needed semiconductor elements such as transistors, etc. However, as other layers are deposited on the substrate during the remaining steps, the resulting multi-layered structure becomes susceptible to peeling or breakage at the edge because of being exposed to handling at the edge. In high density, highly integrated IC's, there may be in excess of ten such layers, each differing in material properties. The difference in the properties exacerbates the peeling and breakage due to the difference in the thermal coefficient of expansion, and the adhesion characteristics of one material with respect to the other, and so on. The layered materials can be as diverse as a polycrystalline for a semiconductor layer, a silicon dioxide or silicon nitride for an insulating interlevel layer, or aluminum as a metal interconnecting layer. Depending upon their particular material properties, the behavior of each one these layers vary as a function of the location on a wafer as they are deposited on the wafer. Thus, when dielectric spin-on-glass, SOG, is spun on a wafer, it forms a bead as it advances towards the edge of the wafer. Similarly, some other materials exhibit an abnormal, or thicker growth towards the edge of the wafer. As additional layers are deposited on the wafer, the irregular growths on the edge reinforce each other, thus resulting in a bulbous protrusion which is shown as item (20) in FIG. 1.
Briefly, FIG. 1 is a cross section of a silicon substrate (10) containing MOS-type field effect transistors, or MOSFETs defined by field oxide fields surrounding n+ doped regions, and a polycrystalline gate (11) which are formed by methods well known in the art and as they are not significant to the invention, will not be described in detail here. Before the first metal layer (13) is blanket deposited over the whole wafer and patterned by etching, an interlevel dielectric layer (15), such as a phospho-silicate glass, or PSG, is also blanket deposited covering the whole wafer and etched to form holes to accept metal as connection between levels, all being accomplished by using conventional methods and techniques. The metal layer is then covered by another dielectric interlevel layer, such as spin-on-glass, SOG (17).
It will be observed from FIG. 1a thus far that as each layer is deposited, there is a bulge or hump of that layer within the vicinity of the edge of the wafer. The bulge is especially pronounced when spinning on SOG (17) in the liquid form, and this behavior can be explained in terms of the phenomenon of hydraulic jump encountered in hydrodynamics of fluids, but not discussed here. A number of additional metal interconnect layers may be formed on wafer (10) in the manner described here by depositing alternately metal and dielectric interlevel layers. It will be appreciated that as more layers are formed, more bulging will occur and the now larger bulbous region (20) will be subjected to more increased local stresses during wafer handling, thus resulting in peeling or breakage at the edge of the wafer as depicted in FIG. 2a. For completeness, a silicon nitride layer (19) is also shown in FIGS. 1a and 2a as the final passivation layer deposited in the final step of sealing the wafer from the environment. That also breaks away into small pieces and forms fine dust particles (22), (24) of different sizes as shown in FIG. 2a.
In another approach to reduce the amount of dust particles generated by the wafers itself, a circumferential portion of layers near the edge of the wafer are removed by grinding or etching until the underlying wafer is exposed. As disclosed in U.S. Pat. No. 5,426,073, the removal of the deposited material on the wafer edge reduces dust generation that would have been caused by cracking or abrasion of the same. The wafer edge grinding is accomplished such that the bulbous protrusion (20) of the deposited layers does not remain thereon, and is shaped round an mirror-finished, according to a chamfering process for general semiconductor wafers. After the grinding step, abrasive powder sticking to the wafer or particles of the ground-off wafer, etc., are completely washed away with deionized water. Finally, for providing the mirror finish of the wafer edge, an additional etching step is employed.
In either one of the approaches of grinding and mirror polishing the wafer edge, and/or the subsequent layers deposited on the wafer, it will be appreciated by those skilled in the art that, the mere fact of grinding the materials still introduces dust particles into the manufacturing line. What is needed, therefore, is a method for eliminating, in the first place, the source of the particles, namely, the layers of materials at the peripheral extremities of the wafer, as disclosed in the present invention.